H. Das, M. Rathore, R. Febbo, M. Liehr, N. C. Cady and G. S. Rose

June, 2023

GLSVLSI - Great Lakes Symposium on VLSI

https://www.glsvlsi.org/

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Abstract

Memristors are a suitable candidate to design synapse circuits and neuromorphic systems. Due to device and voltage variability, operating a memristive device with reliability is a big challenge. To enhance the reliability of memristive synapse, RESET failure needs to be considered. In this work, we are focused on RESET failure modeling with RESET voltage variation. Here, the RESET failure is defined as hard failure of the memristive synapse due to a high RESET voltage being applied. The proposed Verilog-A model is derived based on experimental data collected from 1T1R devices, which are fabricated on 65 nm CMOS process. To enhance the reliability of system-level simulation, this device model will provide better guidelines to the designer. In addition, power consumption for a successful RESET operation is 7.065 μW at 1.5 V, which can RESET the memristor resistance from 5 kΩ to 200 kΩ.

Citation Information

Text

author      H. Das and M. Rathore and R. Febbo and M. Liehr and N. C. Cady and G. S. Rose
title       {RFAM}: {RESET-Failure-Aware-Model} for {HfO2}-based Memristor to Enhance the Reliability of Neuromorphic Design
booktitle   GLSVLSI - Great Lakes Symposium on VLSI
month       June
year        2023
pages       131-136
publisher   ACM
url         https://dl.acm.org/doi/10.1145/3583781.3590210
doi         10.1145/3583781.3590210

Bibtex

@INPROCEEDINGS{drf:23:rfam,
    author = "H. Das and M. Rathore and R. Febbo and M. Liehr and N. C. Cady and G. S. Rose",
    title = "{RFAM}: {RESET-Failure-Aware-Model} for {HfO2}-based Memristor to Enhance the Reliability of Neuromorphic Design",
    booktitle = "GLSVLSI - Great Lakes Symposium on VLSI",
    month = "June",
    year = "2023",
    pages = "131-136",
    publisher = "ACM",
    url = "https://dl.acm.org/doi/10.1145/3583781.3590210",
    doi = "10.1145/3583781.3590210"
}