N. N. Chakraborty, H. Das and G. S. Rose

June, 2023

GLSVLSI - Great Lakes Symposium on VLSI

https://www.glsvlsi.org/

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Abstract

Short-term plasticity (STP) is a synaptic modification process found in biological synapses that increases the computational power of the neuronal network. To implement plasticity rules, we use a memristor-based synapse due to its inherent plasticity. The synapse is designed to operate in the low resistance state (LRS) region using a current-controlled mechanism to account for the device non-idealities encountered at the high resistance state (HRS). In this work, we implement a mixed-signal STP circuit for this synapse design. The STP circuit uses a digital part to generate pulses to initiate the weight change, and an analog part to update the programming voltage. The STP functionality is verified using a 65nm CMOS process, and the performance metrics are reported. Results show that our circuit achieves a great performance in terms of area and power consumption.

Citation Information

Text

author     N. N. Chakraborty and H. Das and G. S. Rose
title      A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse
booktitle   GLSVLSI - Great Lakes Symposium on VLSI
month       June
year        2023
pages       179-182
publisher   ACM
url         https://doi.org/10.1145/3583781.3590283
doi         10.1145/3583781.3590283

Bibtex

@INPROCEEDINGS{cdr:23:mss,
    author = "N. N. Chakraborty and H. Das and G. S. Rose",
    title = "A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse",
    booktitle = "GLSVLSI - Great Lakes Symposium on VLSI",
    month = "June",
    year = "2023",
    pages = "179-182",
    publisher = "ACM",
    url = "https://doi.org/10.1145/3583781.3590283",
    doi = "10.1145/3583781.3590283"
}