M. Adnan and S. Amer and G. S. Rose

May, 2018

IEEE International Symposium on Circuits and Systems (ISCAS)

https://ieeexplore.ieee.org/document/8351840/

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Abstract

Resistive RAM (ReRAM) devices are low power, fast and reliable nanoelectronic memory devices, which have proven to be crucial in both neuromorphic hardware and memory design. Despite their utility, challenges remain in forming and programming these devices before they can be used in a system. This paper builds on a forming circuit, incorporating programming technique in the same circuit in addition to outlining a scan-in approach to programming both CMOS and ReRAM memory elements. The proposed scheme utilizes a single input pin to serially scan-in a bit sequence to program the memory elements, leveraging a digital control circuitry. The suggested protocol is applied to a neuromorphic system to configure synaptic properties to implement a spiking neural network. Lastly, the need for reduction of forming voltage is highlighted with power dissipation data from Spectre simulation.

Citation Information

Text

author          M. Adnan and S. Amer and G. S. Rose
title           A Novel Scan-In Scheme for {CMOS/ReRAM} Programmable Logic Circuits
booktitle       IEEE International Symposium on Circuits and Systems (ISCAS)
month           May
year            2018
doi             10.1109/ISCAS.2018.8351185
url             https://ieeexplore.ieee.org/document/8351185/

Bibtex

@INPROCEEDINGS{ssc:18:hls,
    author = "M. Adnan and S. Amer and G. S. Rose",
    title = "A Novel Scan-In Scheme for {CMOS/ReRAM} Programmable Logic Circuits",
    booktitle = "IEEE International Symposium on Circuits and Systems (ISCAS)",
    month = "May",
    year = "2018",
    doi = "10.1109/ISCAS.2018.8351185",
    url = "https://ieeexplore.ieee.org/document/8351185/"
}