A Bi-Memristor Synapse with Spike-Timing-Dependent Plasticity for On-Chip Learning in Memristive Neuromorphic Systems
Sagarvarma Sayyaparaju, Sherif Amer and Garrett S. Rose
March, 2018
ISQED - 19th International Symposium on Quality Electronic Design
Abstract
Memristors are nanoscale devices that have recently been proposed for use as a synapse in brain-inspired computing systems. In this paper, we present a synapse architecture that utilizes two memristors to implement a non-volatile synaptic weight that can be configured as both positive and negative. The weight of the proposed synapse has an inherent exponential-like dependence on the change in the memristance of the devices, a property that we have capitalized to implement spike-timing-dependent plasticity (STDP) for on-chip learning in spiking neural networks. We discretize the neuron’s spike in time and voltage and show that learning rate can be controlled by the clock frequency used. We show that by modulating the duty cycle of the clock, we can alleviate the detrimental effects of switching rate mismatch in the devices. We also simulated a 3 × 3 crossbar structure and presented the weight updates observed therein, hence demonstrating the feasibility of a crossbar with our synapse. We evaluated the energy consumption per spike of our approach and compared it with those in literature.Citation Information
Text
author S. Sayyaparaju and S. Amer and G. S. Rose
title A Bi-Memristor Synapse with Spike-Timing-Dependent Plasticity for
On-Chip Learning in Memristive Neuromorphic Systems
booktitle ISQED: 19th International Symposium on Quality Electronic Design
month March
year 2018
address Santa Clara, CA
Bibtex
@INPROCEEDINGS{sar:18:bss,
author = "S. Sayyaparaju and S. Amer and G. S. Rose",
title = "A Bi-Memristor Synapse with Spike-Timing-Dependent Plasticity for
On-Chip Learning in Memristive Neuromorphic Systems",
booktitle = "ISQED: 19th International Symposium on Quality Electronic Design",
month = "March",
year = "2018",
address = "Santa Clara, CA"
}