Christopher Daffron

August, 2015

Masters Thesis, University of Tennessee.

http://trace.tennessee.edu/utk_gradthes/3467/

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Abstract

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly reconfigurable and can function as either neurons or synapses with programmable interconnections and parameters. Currently, DANNAs are implemented using a Field Programmable Gate Array (FPGA) and are constrained by this technology. To alleviate these constraints and introduce new and improved features, a semi-custom Very Large Scale Integration (VLSI) implementation has been created. This implementation improves upon the FPGA implementation in three key areas. The density of the array is improved, with 5,625 elements on a single chip using a 130 nm process, compared to approximately 4,225 in the FPGA implementation using a 28 nm process with twice the die size. The speed of the array is improved, with clock speeds ten times faster than is currently implemented on the FPGA, allowing for shorter running times on larger array sizes. Finally, the power consumption of the array is improved by eliminating unused transistors from the design. In addition to alleviating the effects of these three constraints, the VLSI design allows for near real time monitoring of the individual elements in the array.

Citation Information

Text

Daffron, Christopher Paul, "DANNA A Neuromorphic Computing VLSI Chip. " Master's Thesis, University of Tennessee, 2015.
http://trace.tennessee.edu/utk_gradthes/3467

Bibtex

@MISC{cd:15:dan,
  author = "C. P. Daffron",
  title = "{DANNA} A Neuromorphic Computing {VLSI} Chip",
  howpublished = "Masters Thesis, University of Tennessee",
  where = "http://trace.tennessee.edu/utk_gradthes/3467",
  year = "2015"
}