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A VLSI Design for Neuromorphic Computing

Mark E. Dean and Christopher Daffron

July, 2016

IEEE Annual Symposium on VLSI (ISVLSI)

http://ieeexplore.ieee.org/document/7560178

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Abstract

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly reconfigurable and can function as either neurons, synapses or fan-out elements with programmable interconnections and parameters. Currently, DANNAs are implemented using Field Programmable Gate Arrays (FPGAs) and are constrained in capacity and performance by this technology. To alleviate these constraints and introduce new and improved features, a semi-custom Very Large Scale Integration (VLSI) design has been created. This VLSI design improves upon the FPGA implementations in three key areas: 50x improvement in element capacity, 10x improvement in clock speed, and a significant reduction in power consumption. Finally, the VLSI design allows for near real time monitoring of the individual elements in the array.

Citation Information

Text


author     M. E. Dean and C. Daffron
title      A {VLSI} Design for Neuromorphic Computing
booktitle  IEEE Annual Symposium on VLSI (ISVLSI) 
month      July
year       2016
publisher  EEE
doi        10.1109/ISVLSI.2016.81
where      http://ieeexplore.ieee.org/document/7560178/

Bibtex


@INPROCEEDINGS{dd:16:vlsi,
    author = "M. E. Dean and C. Daffron",
    title = "A {VLSI} Design for Neuromorphic Computing",
    booktitle = "IEEE Annual Symposium on VLSI (ISVLSI) ",
    month = "July",
    year = "2016",
    publisher = "IEEE",
    doi = "10.1109/ISVLSI.2016.81",
    where = "http://ieeexplore.ieee.org/document/7560178/"
}